1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly relates to a semiconductor device having a structure in which a source region and a drain region are elevated from the surface of a silicon substrate, that is, having elevated source/drain or raised source/drain, which is used in an SoC (System on Chip) and the like, and a method for manufacturing the same.
2. Related Background Art
With the miniaturization and speeding up of a semiconductor element, salicide (Self Aligned Silicide) technology for forming a high melting point metal silicide (Co silicide, Ni silicide, or the like) film on source and-drain diffusion regions in a self-aligned manner is widely used for an element structure especially for the SoC and the like. The depths of the source and drain diffusion regions are scaled with the miniaturization and speeding up of the semiconductor element, which causes the need for forming the depths of the source and drain diffusion regions more shallowly. The salicide technology utilizes a phenomenon in which a high melting point metal film shows a silicide formation reaction while consuming a silicon semiconductor substrate, which causes a problem that junction leakage occurs by a junction being made shallower due to variations in consumed silicon film thickness in the semiconductor substrate, diffusion of high melting point metal atoms into the semiconductor substrate, and so on. Because of such a problem, scaling to make the junction depth shallower has been difficult in the existing salicide technology.
To solve this problem, it is proposed to form epitaxial silicon in a source region and a drain region at the surface of the semiconductor substrate. Namely, an epitaxial silicon film is formed on the source region and the drain region, then impurity ions are implanted into the surface of the semiconductor substrate, and subsequently a high melting point metal film is formed and silicided, so that the formation of salicide and the formation of a junction in a shallow region from the surface of the semiconductor substrate are compatible.
The aforementioned technology utilizing a structure in which the source region and the drain region are elevated from the original surface of the semiconductor substrate is called elevated source/drain technology or raised source/drain technology.
FIG. 1 shows a MOS transistor using related elevated source/drain technology. A silicon semiconductor substrate 12 includes an element isolation insulating film 10A, and a gate electrode 14 having an SiN/polysilicon stacked structure is formed on the silicon semiconductor substrate 12 with a gate oxide film 13 therebetween. A gate sidewall SiO2 16 and a gate sidewall SiN 18 are formed at a sidewall of the gate electrode 14. A diffusion region 19 is formed in each of a source region and a drain region by ion implantation and annealing.
Then, as shown in FIG. 2, an epitaxial silicon film 20 made of single-crystal silicon is formed on the source diffusion region 19 and the drain diffusion region 19 by an epitaxial growth method. At this time, a facet sometimes appears at the lower end of the gate sidewall, and as an example of measures therefor, a method disclosed in Japanese Patent Laid-open No. 2000-49348 (Patent Document 1) can prevent the facet from appearing.
However, as shown in FIG. 2, even if the aforementioned method is employed, a facet 22 is formed at an interface of the epitaxial silicon film 20 with the element isolation insulating film 10, which sometimes causes a problem such as a short circuit or junction leakage. For this problem, a method of solving the problem by the installation of a stopper film, for example, by a method disclosed in Japanese Patent Laid-open No. 2000-260952 (Patent Document 2) is proposed. However, the surface of the element isolation insulating film 10 is generally higher or lower than the surface of the semiconductor substrate 12, and hence, when the surface of the element isolation insulating film 10 is higher than the surface of the semiconductor substrate 12 as shown in FIG. 2, there arises a problem that the facet 22 such as shown in FIG. 2 is formed. On the other hand, when the surface of the element isolation insulating film 10 is lower than the surface of the semiconductor substrate 12, there arises a problem that the facet 22 such as shown in FIG. 3 is formed. Additionally, when the stopper film is SiO2, there arises a problem that a similar facet is formed.
Moreover, in Japanese Patent Laid-open No. 2002-368227 (Patent Document 3) and U.S. Pat. No. 6,326,281 (Patent Document 4) , a method of directly forming SiN in an element isolation trench is proposed, but this method has a problem that the element isolation withstand voltage deteriorates due to charge injection into an SiN film or strong stress possessed by the SiN film.
As can be seen from the above description, the related arts have a problem that a facet appears in the epitaxial silicon film 20 formed on the source region and the drain region.